We present an analogue front-end for an ISFET sensor with a programmable linear pulse frequency output. The CMOS chip was designed in 0.18 µm technology and electrically characterized. A Veriloga model was used to simulate the ISFET interface with a sensitivity of 30 mV/pH for a Si 3 N 4 membrane. The architecture provides a pulse signal with a 50% duty cycle which encodes a frequency related to the pH of a solution. The linear sensitivity for a ΔV of 600mV in the control circuit is 17.3 kHz/pH, with a minimum and maximum sensitivity of 11.6 - 50.66 kHz/pH, respectively, depending on the setup conditions. The simulation results show a robust and power efficient architecture with a power consumption of 144.2 µW, and a stable response against a ~25% decrease in the power supply.
|Conference||2021 IEEE Sensors|
|Period||31/10/21 → 3/11/21|