Linear Pulse-Frequency Modulator ISFET with a Wide Supply Range

Jose Cortes-guzman; Andreas Tsiamis; David R. S. Cumming; Srinjoy Mitra

doi:10.1109/SENSORS47087.2021.9639752

Linear Pulse-Frequency Modulator ISFET with a Wide Supply Range

Jose Cortes-guzman, Andreas Tsiamis, David R. S. Cumming, Srinjoy Mitra

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract / Description of output

We present an analogue front-end for an ISFET sensor with a programmable linear pulse frequency output. The CMOS chip was designed in 0.18 µm technology and electrically characterized. A Veriloga model was used to simulate the ISFET interface with a sensitivity of 30 mV/pH for a Si 3 N 4 membrane. The architecture provides a pulse signal with a 50% duty cycle which encodes a frequency related to the pH of a solution. The linear sensitivity for a ΔV of 600mV in the control circuit is 17.3 kHz/pH, with a minimum and maximum sensitivity of 11.6 - 50.66 kHz/pH, respectively, depending on the setup conditions. The simulation results show a robust and power efficient architecture with a power consumption of 144.2 µW, and a stable response against a ~25% decrease in the power supply.

Original language	English
Title of host publication	2021 IEEE Sensors
Publisher	IEEE
Pages	1-4
ISBN (Electronic)	978-1-7281-9501-8
DOIs	https://doi.org/10.1109/SENSORS47087.2021.9639752
Publication status	Published - 17 Dec 2021
Event	2021 IEEE Sensors - Sydney, Australia Duration: 31 Oct 2021 → 3 Nov 2021

Publication series

Name	IEEE Sensors
Publisher	IEEE
Volume	2021
ISSN (Print)	1930-0395
ISSN (Electronic)	2168-9229

Conference

Conference	2021 IEEE Sensors
Period	31/10/21 → 3/11/21

Access to Document

10.1109/SENSORS47087.2021.9639752

https://ieeexplore.ieee.org/document/9639752/

Cite this

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title = "Linear Pulse-Frequency Modulator ISFET with a Wide Supply Range",

abstract = "We present an analogue front-end for an ISFET sensor with a programmable linear pulse frequency output. The CMOS chip was designed in 0.18 µm technology and electrically characterized. A Veriloga model was used to simulate the ISFET interface with a sensitivity of 30 mV/pH for a Si 3 N 4 membrane. The architecture provides a pulse signal with a 50% duty cycle which encodes a frequency related to the pH of a solution. The linear sensitivity for a ΔV of 600mV in the control circuit is 17.3 kHz/pH, with a minimum and maximum sensitivity of 11.6 - 50.66 kHz/pH, respectively, depending on the setup conditions. The simulation results show a robust and power efficient architecture with a power consumption of 144.2 µW, and a stable response against a ~25% decrease in the power supply.",

author = "Jose Cortes-guzman and Andreas Tsiamis and Cumming, {David R. S.} and Srinjoy Mitra",

note = "Proxy DOA to exclude from REF. Original DOA 17/08/21; 2021 IEEE Sensors ; Conference date: 31-10-2021 Through 03-11-2021",

year = "2021",

month = dec,

day = "17",

doi = "10.1109/SENSORS47087.2021.9639752",

language = "English",

series = "IEEE Sensors",

publisher = "IEEE",

pages = "1--4",

booktitle = "2021 IEEE Sensors",

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TY - GEN

T1 - Linear Pulse-Frequency Modulator ISFET with a Wide Supply Range

AU - Cortes-guzman, Jose

AU - Tsiamis, Andreas

AU - Cumming, David R. S.

AU - Mitra, Srinjoy

N1 - Proxy DOA to exclude from REF. Original DOA 17/08/21

PY - 2021/12/17

Y1 - 2021/12/17

N2 - We present an analogue front-end for an ISFET sensor with a programmable linear pulse frequency output. The CMOS chip was designed in 0.18 µm technology and electrically characterized. A Veriloga model was used to simulate the ISFET interface with a sensitivity of 30 mV/pH for a Si 3 N 4 membrane. The architecture provides a pulse signal with a 50% duty cycle which encodes a frequency related to the pH of a solution. The linear sensitivity for a ΔV of 600mV in the control circuit is 17.3 kHz/pH, with a minimum and maximum sensitivity of 11.6 - 50.66 kHz/pH, respectively, depending on the setup conditions. The simulation results show a robust and power efficient architecture with a power consumption of 144.2 µW, and a stable response against a ~25% decrease in the power supply.

AB - We present an analogue front-end for an ISFET sensor with a programmable linear pulse frequency output. The CMOS chip was designed in 0.18 µm technology and electrically characterized. A Veriloga model was used to simulate the ISFET interface with a sensitivity of 30 mV/pH for a Si 3 N 4 membrane. The architecture provides a pulse signal with a 50% duty cycle which encodes a frequency related to the pH of a solution. The linear sensitivity for a ΔV of 600mV in the control circuit is 17.3 kHz/pH, with a minimum and maximum sensitivity of 11.6 - 50.66 kHz/pH, respectively, depending on the setup conditions. The simulation results show a robust and power efficient architecture with a power consumption of 144.2 µW, and a stable response against a ~25% decrease in the power supply.

U2 - 10.1109/SENSORS47087.2021.9639752

DO - 10.1109/SENSORS47087.2021.9639752

M3 - Conference contribution

T3 - IEEE Sensors

SP - 1

EP - 4

BT - 2021 IEEE Sensors

PB - IEEE

T2 - 2021 IEEE Sensors

Y2 - 31 October 2021 through 3 November 2021

ER -

Linear Pulse-Frequency Modulator ISFET with a Wide Supply Range

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