Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO

Cristian Sestito; Georgios Papandroulidakis; Patrick Foster; Spyros Stathopoulos; Shady Agwa; Themis Prodromakis

doi:10.1109/ISCAS56072.2025.11044243

Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO

Cristian Sestito^*
, Georgios Papandroulidakis
, Patrick Foster
, Spyros Stathopoulos
, Shady Agwa
, Themis Prodromakis

^*Corresponding author for this work

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this demonstration, we present a hardware/software co-design methodology for Convolutional Neural Networks, where the classification section is managed through Resistive RAMs (RRAMs). To this aim, RRAM arrays are mounted onto the ArC TWO instrumentation board, which is interfaced to a laptop. A software Python front-end executes convolutional layers for feature extraction, generates stimuli for RRAMs, and controls the instrumentation board. As a proof of concept, handwritten digits classification is exhibited.

Original language	English
Title of host publication	2025 IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	Institute of Electrical and Electronics Engineers
Number of pages	1
ISBN (Electronic)	9798350356830
DOIs	https://doi.org/10.1109/ISCAS56072.2025.11044243
Publication status	Published - 27 Jun 2025
Event	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, United Kingdom Duration: 25 May 2025 → 28 May 2025

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Country/Territory	United Kingdom
City	London
Period	25/05/25 → 28/05/25

Access to Document

10.1109/ISCAS56072.2025.11044243

Accepted_PaperAccepted author manuscript, 1.01 MBLicence: Creative Commons: Attribution (CC-BY)

Cite this

Sestito, C., Papandroulidakis, G., Foster, P., Stathopoulos, S., Agwa, S., & Prodromakis, T. (2025). Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO. In 2025 IEEE International Symposium on Circuits and Systems (ISCAS) (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS56072.2025.11044243

Sestito, Cristian ; Papandroulidakis, Georgios ; Foster, Patrick et al. / Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO. 2025 IEEE International Symposium on Circuits and Systems (ISCAS). Institute of Electrical and Electronics Engineers, 2025. (Proceedings - IEEE International Symposium on Circuits and Systems).

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title = "Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO",

abstract = "In this demonstration, we present a hardware/software co-design methodology for Convolutional Neural Networks, where the classification section is managed through Resistive RAMs (RRAMs). To this aim, RRAM arrays are mounted onto the ArC TWO instrumentation board, which is interfaced to a laptop. A software Python front-end executes convolutional layers for feature extraction, generates stimuli for RRAMs, and controls the instrumentation board. As a proof of concept, handwritten digits classification is exhibited.",

author = "Cristian Sestito and Georgios Papandroulidakis and Patrick Foster and Spyros Stathopoulos and Shady Agwa and Themis Prodromakis",

year = "2025",

month = jun,

day = "27",

doi = "10.1109/ISCAS56072.2025.11044243",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers",

booktitle = "2025 IEEE International Symposium on Circuits and Systems (ISCAS)",

address = "United States",

note = "2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",

}

Sestito, C , Papandroulidakis, G , Foster, P , Stathopoulos, S, Agwa, S & Prodromakis, T 2025, Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO. in 2025 IEEE International Symposium on Circuits and Systems (ISCAS). Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers, 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, 25/05/25. https://doi.org/10.1109/ISCAS56072.2025.11044243

Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO. / Sestito, Cristian ; Papandroulidakis, Georgios ; Foster, Patrick et al.
2025 IEEE International Symposium on Circuits and Systems (ISCAS). Institute of Electrical and Electronics Engineers, 2025. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO

AU - Sestito, Cristian

AU - Papandroulidakis, Georgios

AU - Foster, Patrick

AU - Stathopoulos, Spyros

AU - Agwa, Shady

AU - Prodromakis, Themis

PY - 2025/6/27

Y1 - 2025/6/27

N2 - In this demonstration, we present a hardware/software co-design methodology for Convolutional Neural Networks, where the classification section is managed through Resistive RAMs (RRAMs). To this aim, RRAM arrays are mounted onto the ArC TWO instrumentation board, which is interfaced to a laptop. A software Python front-end executes convolutional layers for feature extraction, generates stimuli for RRAMs, and controls the instrumentation board. As a proof of concept, handwritten digits classification is exhibited.

AB - In this demonstration, we present a hardware/software co-design methodology for Convolutional Neural Networks, where the classification section is managed through Resistive RAMs (RRAMs). To this aim, RRAM arrays are mounted onto the ArC TWO instrumentation board, which is interfaced to a laptop. A software Python front-end executes convolutional layers for feature extraction, generates stimuli for RRAMs, and controls the instrumentation board. As a proof of concept, handwritten digits classification is exhibited.

UR - https://doi.org/10.1109/ISCAS56072.2025.11044243

UR - https://www.scopus.com/pages/publications/105010623220

U2 - 10.1109/ISCAS56072.2025.11044243

DO - 10.1109/ISCAS56072.2025.11044243

M3 - Conference contribution

AN - SCOPUS:105010623220

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2025 IEEE International Symposium on Circuits and Systems (ISCAS)

PB - Institute of Electrical and Electronics Engineers

T2 - 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025

Y2 - 25 May 2025 through 28 May 2025

ER -

Sestito C , Papandroulidakis G , Foster P , Stathopoulos S, Agwa S, Prodromakis T. Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO. In 2025 IEEE International Symposium on Circuits and Systems (ISCAS). Institute of Electrical and Electronics Engineers. 2025. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS56072.2025.11044243

Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO

Abstract

Publication series

Conference

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AI for Productive Research & Innovation in eLectronics (APRIL)

ProSensing: Low-Power, High-Speed, Adaptable Processing-In-Sensing Capability

AI MeTLLE: Memristive Technologies for Lifelong Learning Embedded AI Hardware (AI MeTLLE)

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Live Demonstration: Hardware/Software Co-Design to Exploit RRAM Programmability for Emerging Edge Classification Using ArC TWO

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Projects

AI for Productive Research & Innovation in eLectronics (APRIL)

ProSensing: Low-Power, High-Speed, Adaptable Processing-In-Sensing Capability

AI MeTLLE: Memristive Technologies for Lifelong Learning Embedded AI Hardware (AI MeTLLE)

Cite this