Low power implementation for minimum norm sorting and block upper tri-angularization of matrices used in MIMO wireless systems

Zahid Khan*, Tughrul Arslan, John S. Thompson, Ahmet T. Erdogan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumption. This paper proposes an area and power efficient VLSI architecture that can serve the dual purpose of minimum norm sorting of rows as well as upper/lower block tri-angularization of matrices. The resources inside the architecture are shared among both operations and only primitive computations are used. Results indicate saving in silicon real estate as well as power consumption compared to previous architecture without degrading performance.

Original languageEnglish
Title of host publicationProceedings - 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems
Pages744-749
Number of pages6
DOIs
Publication statusPublished - 2007
Event20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07 - Bangalore, India
Duration: 6 Jan 200710 Jan 2007

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Conference

Conference20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems, VLSID'07
Country/TerritoryIndia
CityBangalore
Period6/01/0710/01/07

Fingerprint

Dive into the research topics of 'Low power implementation for minimum norm sorting and block upper tri-angularization of matrices used in MIMO wireless systems'. Together they form a unique fingerprint.

Cite this