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Abstract / Description of output
This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor's advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Early online date||17 May 2023|
|Publication status||Published - 1 Sept 2023|
Keywords / Materials (for Non-textual outputs)
- SAR ADC
- hybrid DAC
- memristor-assisted calibration
1/05/22 → 31/12/29
Prodromakis, T., Constandinou, T. G., Dudek, P., Koch, D. & Papavassiliou, C.
1/05/22 → 30/09/23