Abstract / Description of output
The connection of a number of parallel processors by means of a common shared store suffers from two fundamental problems. Firstly there is the difficulty of providing adequate memory bandwidth to support large numbers of processors, all of which in principle could be contending for the same memory module. Secondly, where processors attempt to coordinate their activities through synchronisation variables held in common memory, the inefficiencies due to processors idling in a tight loop, and the saturation of vulnerable links in the processor-memory network can lead to poor performance.
| Original language | English |
|---|---|
| Title of host publication | Architecture of High Performance Computers Volume II |
| Subtitle of host publication | Array processors and multiprocessor systems |
| Place of Publication | New York, NY |
| Publisher | Springer New York |
| Pages | 141-167 |
| Number of pages | 27 |
| ISBN (Electronic) | 978-1-4899-6701-5 |
| ISBN (Print) | 978-1-4899-6703-9 |
| DOIs | |
| Publication status | Published - 1989 |