Abstract
Micronets model processor architectures as a network of communicating resources, in contrast to the traditional one of a linear pipeline. Micronets distribute the control to the functional units, which enables the exploitation of fine-grain concurrency between instructions. The overhead due to asynchrony is hidden with the four-phase protocol being used to implement scoreboarding and hazard avoidance mechanisms, without incurring additional control costs. This paper demonstrates the feasibility of micronet-based processors. Results are presented for SPICE-level simulations of a 0.7 μm CMOS implementation of a datapath. The relationships between micronets and both the compiler and the computer architecture are also explored
Original language | English |
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Title of host publication | Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 190-199 |
Number of pages | 10 |
ISBN (Print) | 0-8186-7098-3 |
DOIs | |
Publication status | Published - 1 May 1995 |
Keywords / Materials (for Non-textual outputs)
- computer architecture
- pipeline processing
- SPICE-level simulations
- asynchronous processor architectures
- communicating resources
- decentralising control
- fine-grain concurrency
- four-phase protocol
- hazard avoidance mechanisms
- micronets
- processor architectures
- Communication system control
- Computer architecture
- Computer science
- Concurrent computing
- Costs
- Electronic mail
- Hazards
- Pipelines
- Process control
- Resource management