MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance

Pavlos Petoumenos, Georgia Psychou, Stefanos Kaxiras, Juan Manuel Cebrian Gonzalez, Juan Luis Aragon

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Several techniques aiming to improve power-efficiency (measured as EDP) in out-of-order cores trade energy with performance. Prime exam ples are the techniques to resize the instruction queue (IQ). While most of them produce good results, they fail to take into account that changing the timing of memory accesses can have significant consequences on the memo ry-level parallelism (MLP) of the application and thus incur disproportional performance degradation. We propose a novel mechanism that deals with this realization by collecting fine-grain information about the maximum IQ resiz ing that does not affect the MLP of the program. This information is used to override the resizing enforced by feedback mechanisms when this resizing might reduce MLP. We compare our technique to a previously proposed non-MLP-aware management technique and our results show a significant in crease in EDP savings for most benchmarks of the SPEC2000 suite.
Original languageEnglish
Title of host publicationArchitecture of Computing Systems - ARCS 2010
Subtitle of host publication23rd International Conference, Hannover, Germany, February 22-25, 2010. Proceedings
EditorsChristian Müller-Schloer, Wolfgang Karl, Sami Yehia
Place of PublicationBerlin, Heidelberg
PublisherSpringer Berlin Heidelberg
Number of pages13
ISBN (Electronic)978-3-642-11950-7
ISBN (Print)978-3-642-11949-1
Publication statusPublished - 2010

Publication series

NameLecture Notes in Computer Science
PublisherSpringer Berlin Heidelberg
ISSN (Print)0302-9743


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