Modelling HW/SW Co-Designed Processors

Jose Cano Reyes, A. Brankovic, R. Kumar, D. Zivanovic, D. Pavlou, K. Stavrou, E. Gibert, A. Martinez, G. Dot, F. Latorre

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents DARCO, an extensible platform for modelling HW/SW co-designed pro- cessors with different guest and host ISAs. Its Emulation Software Layer (ESL) provides staged compilation, which translates and optimizes x86 binaries to run on a PowerPC processor. In ad- dition to the functional models, DARCO provides timing simulators and a powerful debugging toolchain. DARCO has a functional emulation speed of 8 million x86 instructions per second
Original languageEnglish
Title of host publicationEighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems
Number of pages4
Publication statusPublished - 2012

Fingerprint Dive into the research topics of 'Modelling HW/SW Co-Designed Processors'. Together they form a unique fingerprint.

Cite this