Multiple-banked Register File Architectures

José-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor generations, as they are expected to increase the issue width (which implies more register ports) and the size of the instruction window (which implies more registers), and to use some kind of multithreading. Under this scenario, the register file access time could be a dominant delay and a pipelined implementation would be desirable to allow for high clock rates. However, a multi-stage register file has severe implications for processor performance (e.g. higher branch misprediction penalty) and complexity (more levels of bypass logic). To tackle these two problems, in this paper we propose a register file architecture composed of multiple banks. In particular we focus on a multi-level organization of the register file, which provides low latency and simple bypass logic. We propose several caching policies and prefetching strategies and demonstrate the potential of this multiple-banked organization. For instance, we show that a two-level organization degrades IPC by 10% and 2% with respect to a non-pipelined single-banked register file, for SpecInt95 and SpecFP95 respectively, but it increases performance by 87% and 92% when the register file access time is factored in.
Original languageEnglish
Title of host publicationProceedings of the 27th Annual International Symposium on Computer Architecture
Place of PublicationNew York, NY, USA
Number of pages10
ISBN (Print)1-58113-232-8
Publication statusPublished - 2000

Publication series

NameISCA '00

Keywords / Materials (for Non-textual outputs)

  • bypass logic, dynamically-scheduled processor, register file architecture, register file cache


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