Multiple-event direct to histogram TDC in 65nm FPGA technology

Neale Dutton, Johannes Vergote, Salvatore Gnecchi, Lindsay Grant, David Lee, Bruce R. Rae, Sara Pellegrini, Robert Henderson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A novel multiple-event Time to Digital Converter (TDC) with direct to histogram output is implemented in a 65nm Xilinx Virtex 5 FPGA. The delay-line based architecture achieves 16.3 ps temporal accuracy over a 2.86ns dynamic range. The measured maximum conversion rate of 6.17 Gsamples/s and the sampling rate of 61.7 Gsamples/s are the highest published in the literature. The system achieves a linearity of -0.9/+3 LSB DNL and -1.5/+5 LSB INL. The TDC is demonstrated in a direct time of flight optical ranging application with 12mm error over a 350mm range
Original languageEnglish
Title of host publicationMicroelectronics and Electronics (PRIME), 2014 10th Conference on Ph.D. Research in
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages5
DOIs
Publication statusPublished - 2 Jul 2014

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