Multiple-event direct to histogram TDC in 65nm FPGA technology

Neale Dutton; Johannes Vergote; Salvatore Gnecchi; Lindsay Grant; David Lee; Bruce R. Rae; Sara Pellegrini; Robert Henderson

doi:10.1109/PRIME.2014.6872727

Multiple-event direct to histogram TDC in 65nm FPGA technology

Neale Dutton, Johannes Vergote, Salvatore Gnecchi, Lindsay Grant, David Lee, Bruce R. Rae, Sara Pellegrini, Robert Henderson

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract / Description of output

A novel multiple-event Time to Digital Converter (TDC) with direct to histogram output is implemented in a 65nm Xilinx Virtex 5 FPGA. The delay-line based architecture achieves 16.3 ps temporal accuracy over a 2.86ns dynamic range. The measured maximum conversion rate of 6.17 Gsamples/s and the sampling rate of 61.7 Gsamples/s are the highest published in the literature. The system achieves a linearity of -0.9/+3 LSB DNL and -1.5/+5 LSB INL. The TDC is demonstrated in a direct time of flight optical ranging application with 12mm error over a 350mm range

Original language	English
Title of host publication	Microelectronics and Electronics (PRIME), 2014 10th Conference on Ph.D. Research in
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Number of pages	5
DOIs	https://doi.org/10.1109/PRIME.2014.6872727
Publication status	Published - 2 Jul 2014

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10.1109/PRIME.2014.6872727

PhD Student Support- as part of the UoE/STMicroelectronic Research Collaboration
Henderson, R.
UK industry, commerce and public corporations
1/01/11 → 29/02/20
Project: Research

Cite this

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title = "Multiple-event direct to histogram TDC in 65nm FPGA technology",

abstract = "A novel multiple-event Time to Digital Converter (TDC) with direct to histogram output is implemented in a 65nm Xilinx Virtex 5 FPGA. The delay-line based architecture achieves 16.3 ps temporal accuracy over a 2.86ns dynamic range. The measured maximum conversion rate of 6.17 Gsamples/s and the sampling rate of 61.7 Gsamples/s are the highest published in the literature. The system achieves a linearity of -0.9/+3 LSB DNL and -1.5/+5 LSB INL. The TDC is demonstrated in a direct time of flight optical ranging application with 12mm error over a 350mm range",

author = "Neale Dutton and Johannes Vergote and Salvatore Gnecchi and Lindsay Grant and David Lee and Rae, {Bruce R.} and Sara Pellegrini and Robert Henderson",

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doi = "10.1109/PRIME.2014.6872727",

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T1 - Multiple-event direct to histogram TDC in 65nm FPGA technology

AU - Dutton, Neale

AU - Vergote, Johannes

AU - Gnecchi, Salvatore

AU - Grant, Lindsay

AU - Lee, David

AU - Rae, Bruce R.

AU - Pellegrini, Sara

AU - Henderson, Robert

PY - 2014/7/2

Y1 - 2014/7/2

N2 - A novel multiple-event Time to Digital Converter (TDC) with direct to histogram output is implemented in a 65nm Xilinx Virtex 5 FPGA. The delay-line based architecture achieves 16.3 ps temporal accuracy over a 2.86ns dynamic range. The measured maximum conversion rate of 6.17 Gsamples/s and the sampling rate of 61.7 Gsamples/s are the highest published in the literature. The system achieves a linearity of -0.9/+3 LSB DNL and -1.5/+5 LSB INL. The TDC is demonstrated in a direct time of flight optical ranging application with 12mm error over a 350mm range

AB - A novel multiple-event Time to Digital Converter (TDC) with direct to histogram output is implemented in a 65nm Xilinx Virtex 5 FPGA. The delay-line based architecture achieves 16.3 ps temporal accuracy over a 2.86ns dynamic range. The measured maximum conversion rate of 6.17 Gsamples/s and the sampling rate of 61.7 Gsamples/s are the highest published in the literature. The system achieves a linearity of -0.9/+3 LSB DNL and -1.5/+5 LSB INL. The TDC is demonstrated in a direct time of flight optical ranging application with 12mm error over a 350mm range

U2 - 10.1109/PRIME.2014.6872727

DO - 10.1109/PRIME.2014.6872727

M3 - Conference contribution

BT - Microelectronics and Electronics (PRIME), 2014 10th Conference on Ph.D. Research in

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

Multiple-event direct to histogram TDC in 65nm FPGA technology

Abstract / Description of output

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PhD Student Support- as part of the UoE/STMicroelectronic Research Collaboration

Cite this