Multiprocessor Architecture

R. N. Ibbett; N. P. Topham

doi:10.1007/978-1-4899-6701-5_6

Multiprocessor Architecture

R. N. Ibbett, N. P. Topham

School of Informatics

Research output: Chapter in Book/Report/Conference proceeding › Chapter

Abstract

In the first volume we examined the range of techniques which are employed in high-performance architectures to improve the throughput within a single processor. These techniques included pipelining, multiple function units and a variety of mechanisms designed to meet the necessary memory throughput and latency requirements. However, the so-called ‘von Neumann bottleneck’, which is the fundamental limit imposed on sequential processing by the rate at which information can be moved across the boundary between processor and memory, limits both the rate at which instructions can be issued and the rate at which operands can be supplied.

Original language	English
Title of host publication	Architecture of High Performance Computers Volume II
Subtitle of host publication	Array processors and multiprocessor systems
Place of Publication	New York, NY
Publisher	Springer New York
Pages	83-108
Number of pages	26
ISBN (Electronic)	978-1-4899-6701-5
ISBN (Print)	978-1-4899-6703-9
DOIs	https://doi.org/10.1007/978-1-4899-6701-5_6
Publication status	Published - 1989

Access to Document

10.1007/978-1-4899-6701-5_6

http://link.springer.com/chapter/10.1007/978-1-4899-6701-5_6

Cite this

@inbook{56e7e4ff9e864785a747ddc851eef1ab,

title = "Multiprocessor Architecture",

abstract = "In the first volume we examined the range of techniques which are employed in high-performance architectures to improve the throughput within a single processor. These techniques included pipelining, multiple function units and a variety of mechanisms designed to meet the necessary memory throughput and latency requirements. However, the so-called {\textquoteleft}von Neumann bottleneck{\textquoteright}, which is the fundamental limit imposed on sequential processing by the rate at which information can be moved across the boundary between processor and memory, limits both the rate at which instructions can be issued and the rate at which operands can be supplied.",

author = "Ibbett, {R. N.} and Topham, {N. P.}",

year = "1989",

doi = "10.1007/978-1-4899-6701-5_6",

language = "English",

isbn = "978-1-4899-6703-9",

pages = "83--108",

booktitle = "Architecture of High Performance Computers Volume II",

publisher = "Springer New York",

address = "United States",

}

TY - CHAP

T1 - Multiprocessor Architecture

AU - Ibbett, R. N.

AU - Topham, N. P.

PY - 1989

Y1 - 1989

N2 - In the first volume we examined the range of techniques which are employed in high-performance architectures to improve the throughput within a single processor. These techniques included pipelining, multiple function units and a variety of mechanisms designed to meet the necessary memory throughput and latency requirements. However, the so-called ‘von Neumann bottleneck’, which is the fundamental limit imposed on sequential processing by the rate at which information can be moved across the boundary between processor and memory, limits both the rate at which instructions can be issued and the rate at which operands can be supplied.

AB - In the first volume we examined the range of techniques which are employed in high-performance architectures to improve the throughput within a single processor. These techniques included pipelining, multiple function units and a variety of mechanisms designed to meet the necessary memory throughput and latency requirements. However, the so-called ‘von Neumann bottleneck’, which is the fundamental limit imposed on sequential processing by the rate at which information can be moved across the boundary between processor and memory, limits both the rate at which instructions can be issued and the rate at which operands can be supplied.

U2 - 10.1007/978-1-4899-6701-5_6

DO - 10.1007/978-1-4899-6701-5_6

M3 - Chapter

SN - 978-1-4899-6703-9

SP - 83

EP - 108

BT - Architecture of High Performance Computers Volume II

PB - Springer New York

CY - New York, NY

ER -

Multiprocessor Architecture

Abstract

Access to Document

Fingerprint

Cite this