Multiprocessor Architecture

R. N. Ibbett, N. P. Topham

Research output: Chapter in Book/Report/Conference proceedingChapter


In the first volume we examined the range of techniques which are employed in high-performance architectures to improve the throughput within a single processor. These techniques included pipelining, multiple function units and a variety of mechanisms designed to meet the necessary memory throughput and latency requirements. However, the so-called ‘von Neumann bottleneck’, which is the fundamental limit imposed on sequential processing by the rate at which information can be moved across the boundary between processor and memory, limits both the rate at which instructions can be issued and the rate at which operands can be supplied.
Original languageEnglish
Title of host publicationArchitecture of High Performance Computers Volume II
Subtitle of host publicationArray processors and multiprocessor systems
Place of PublicationNew York, NY
PublisherSpringer New York
Number of pages26
ISBN (Electronic)978-1-4899-6701-5
ISBN (Print)978-1-4899-6703-9
Publication statusPublished - 1989


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