In the first volume we examined the range of techniques which are employed in high-performance architectures to improve the throughput within a single processor. These techniques included pipelining, multiple function units and a variety of mechanisms designed to meet the necessary memory throughput and latency requirements. However, the so-called ‘von Neumann bottleneck’, which is the fundamental limit imposed on sequential processing by the rate at which information can be moved across the boundary between processor and memory, limits both the rate at which instructions can be issued and the rate at which operands can be supplied.
|Title of host publication||Architecture of High Performance Computers Volume II|
|Subtitle of host publication||Array processors and multiprocessor systems|
|Place of Publication||New York, NY|
|Publisher||Springer New York|
|Number of pages||26|
|Publication status||Published - 1989|