Netrace: Dependency-Driven Trace-Based Network-on-Chip Simulation

J Hestness, Boris Grot, Stephen W. Keckler

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Chip multiprocessors (CMPs) and systems-on-chip (SOCs) are expected to grow in core count from a few today to hundreds or more. Since efficient on-chip communication is a primary factor in the performance of large core-count systems, the research community has directed substantial attention to networks-on-chip (NOCs). Current NOC evaluation methodologies include analytical modeling, network simulation, and full-system simulation. However, as core count and system complexity grow, the deficiencies of each of these methods will limit their ability to meet the demands of developers and researchers. Developing efficient NOCs requires high-fidelity, low-overhead NOC evaluation techniques and metrics. To address these challenges, this paper describes a new trace-based network simulation methodology that captures dependencies between network messages observed in full-system simulation of multithreaded applications. We also introduce Netrace, a library of tools and traces that enables
targeted NOC simulators to track and replay network messages and their dependencies.
Original languageEnglish
Title of host publication3rd International Workshop on Network on Chip Architectures (NoCArc) 2010
Number of pages6
Publication statusPublished - 2010


Dive into the research topics of 'Netrace: Dependency-Driven Trace-Based Network-on-Chip Simulation'. Together they form a unique fingerprint.

Cite this