In fault-tolerant FPGA systems, the internal reconfiguration capabilities supported in modern FPGAs is commonly utilized for enhanced fault mitigation. In such systems, faults in the internal configuration controller can degrade the fault-tolerance of the system and in extreme cases can lead to additional faults injected into the system. In this paper we present different methods for enhancing the reliability of internal configuration controllers in FPGAs. We demonstrate the design of a custom ICAP controller for Xilinx Virtex FPGAs and compare the reliability and area overhead for Triple Modular Redundancy (TMR), Dual Modular Redundancy (DMR) and Cyclic Redundancy Check (CRC) design schemes. We also evaluate the effectiveness of internal readback and external configuration memory scrubbing and show how a combination of the two methods can reduce the number of single points of failure in the system.