On Low-Leakage CMOS Switches

Bo Wang, Shiwei Wang, Man-Kay Law

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Continuing CMOS process scaling to favor the design of high-performance digital systems has resulted in many issues for precision analog design, and one of which is the detrimental transistor leakage. This paper focuses on the analysis and design of low-leakage switches. Specifically, transistor leak-age mechanisms and the evolution of low-leakage switch design techniques are revisited. Different schemes to achieve transistor channel and body leakage reduction are discussed. In addition, we propose a low-leakage switch that can operate for a wide temperature range. At 200 ◦ C, it achieves 130 × and 8 × lower leakage than the transmission gate and the popular analog T-switch, respectively.
Original languageUndefined/Unknown
Title of host publication2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
PublisherIEEE
Pages1-5
Number of pages5
DOIs
Publication statusPublished - 13 Sept 2021
Event2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) - Online
Duration: 9 Aug 202111 Aug 2021
https://www.mwscas2021.org/

Conference

Conference2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)
Period9/08/2111/08/21
Internet address

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