On the low-power implementation of FIR filtering structures on single multiplier DSPs

The authors present three multiplication schemes for the low-power implementation of finite-impulse response (FIR) filters on single multiplier complementary metal-oxide-semiconductor (CMOS) digital signal processors (DSPs). The schemes achieve power reduction through the minimization of switching activity at one or both inputs of the multiplier. In addition, these schemes are characterized by their flexibility since they tradeoff implementation cost against power consumption. Results are provided for a number of example FIR filters demonstrating power savings ranging from 20% with schemes which can be implemented on existing common DSPs, and up to 51% with schemes using enhanced DSP architectures.