On the performance evaluation of asynchronous processor architectures

D. K. Arvind, V. E. F. Rebello

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper evaluates and analyses the influence of an asynchronous control paradigm on the performance of processor architectures. The idea of a micronet is introduced which models the datapath as a network of concurrent functional units which communicate with each other asynchronously. This allows the efficient exploitation of fine-grained instruction-level parallelism (ILP). A macronet-based asynchronous processor (MAP) architecture is described in Occam2 and simulated in a parallel discrete event simulation environment. Suitable metrics are introduced for measuring the performance of the MAP datapath
Original languageEnglish
Title of host publicationModeling, Analysis, and Simulation of Computer and Telecommunication Systems, 1995. MASCOTS '95., Proceedings of the Third International Workshop on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages5
ISBN (Print)0-8186-6902-0
Publication statusPublished - 1 Jan 1995


  • computer architecture
  • discrete event simulation
  • performance evaluation
  • Occam2
  • asynchronous control paradigm
  • asynchronous processor architectures
  • concurrent functional units
  • fine-grained instruction-level parallelism
  • micronet
  • parallel discrete event simulation environment
  • Asynchronous circuits
  • Circuit synthesis
  • Computer architecture
  • Computer science
  • Delay
  • Discrete event simulation
  • Performance analysis
  • Pipelines
  • Process design
  • Synchronization


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