OneDSP: A unifying DSP architecture for Systems-on-a-Chip

Kar-Lik Wong; N. Topham

doi:10.1109/ICASSP.2002.5745482

OneDSP: A unifying DSP architecture for Systems-on-a-Chip

Kar-Lik Wong, N. Topham

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Siroyan develops and licenses DSP cores and related software development tools. Its first architecture, the OneDSP, disclosed in October 2001, is a unifying digital signal processor architecture designed from scratch for the high performance and flexibility demanded by next generation System-on-a-Chip (SoC) designs. Its configurable, clustered VLIW architecture optimizes hardware resources to exploit the instruction level parallelism (ILP) that exists in DSP applications. The industrial-strength tool-chain ease porting application and SoC integration. Using a parallel FFT algorithm as an example, we demonstrate that the performance of OneDSP can scale linearly with increasing number of clusters. Benchmark figures are included to show the highly competitive performance of the architecture.

Original language	English
Title of host publication	Acoustics, Speech, and Signal Processing (ICASSP), 2002 IEEE International Conference on
Pages	IV-3792-IV-3795
Number of pages	4
Volume	4
DOIs	https://doi.org/10.1109/ICASSP.2002.5745482
Publication status	Published - 1 May 2002

Keywords

Digital signal processing
VLIW

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title = "OneDSP: A unifying DSP architecture for Systems-on-a-Chip",

abstract = "Siroyan develops and licenses DSP cores and related software development tools. Its first architecture, the OneDSP, disclosed in October 2001, is a unifying digital signal processor architecture designed from scratch for the high performance and flexibility demanded by next generation System-on-a-Chip (SoC) designs. Its configurable, clustered VLIW architecture optimizes hardware resources to exploit the instruction level parallelism (ILP) that exists in DSP applications. The industrial-strength tool-chain ease porting application and SoC integration. Using a parallel FFT algorithm as an example, we demonstrate that the performance of OneDSP can scale linearly with increasing number of clusters. Benchmark figures are included to show the highly competitive performance of the architecture.",

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N2 - Siroyan develops and licenses DSP cores and related software development tools. Its first architecture, the OneDSP, disclosed in October 2001, is a unifying digital signal processor architecture designed from scratch for the high performance and flexibility demanded by next generation System-on-a-Chip (SoC) designs. Its configurable, clustered VLIW architecture optimizes hardware resources to exploit the instruction level parallelism (ILP) that exists in DSP applications. The industrial-strength tool-chain ease porting application and SoC integration. Using a parallel FFT algorithm as an example, we demonstrate that the performance of OneDSP can scale linearly with increasing number of clusters. Benchmark figures are included to show the highly competitive performance of the architecture.

AB - Siroyan develops and licenses DSP cores and related software development tools. Its first architecture, the OneDSP, disclosed in October 2001, is a unifying digital signal processor architecture designed from scratch for the high performance and flexibility demanded by next generation System-on-a-Chip (SoC) designs. Its configurable, clustered VLIW architecture optimizes hardware resources to exploit the instruction level parallelism (ILP) that exists in DSP applications. The industrial-strength tool-chain ease porting application and SoC integration. Using a parallel FFT algorithm as an example, we demonstrate that the performance of OneDSP can scale linearly with increasing number of clusters. Benchmark figures are included to show the highly competitive performance of the architecture.

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KW - VLIW

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DO - 10.1109/ICASSP.2002.5745482

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BT - Acoustics, Speech, and Signal Processing (ICASSP), 2002 IEEE International Conference on

ER -

OneDSP: A unifying DSP architecture for Systems-on-a-Chip

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Keywords

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