Optimisation of an FPGA Credit Default Swap engine by embracing dataflow techniques

Nick Brown*, Mark Klaisoongnoen, Oliver Brown

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Quantitative finance is the use of mathematical models to analyse financial markets and securities. Typically requiring significant amounts of computation, an important question is the role that novel architectures can play in accelerating these models in the future on HPC machines. In this paper we explore the optimisation of an existing, open source, FPGA based Credit Default Swap (CDS) engine using High Level Synthesis (HLS). Developed by Xilinx, and part of their open source Vitis libraries, the implementation of this engine currently favours flexibility and ease of integration over performance.We explore redesigning the engine to fully embrace the dataflow approach, ultimately resulting in an engine which is around eight times faster on an Alveo U280 FPGA than the original Xilinx library version. We then compare five of our engines on the U280 against a 24-core Xeon Platinum Cascade Lake CPU, outperforming the CPU by around 1.55 times, with the FPGA consuming 4.7 times less power and delivering around seven times the power efficiency of the CPU.
Original languageEnglish
Title of host publication2021 IEEE International Conference on Cluster Computing (CLUSTER)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages4
ISBN (Electronic)978-1-7281-9666-4
ISBN (Print)978-1-7281-9667-1
Publication statusE-pub ahead of print - 13 Oct 2021
EventIEEE Cluster 2021 - Virtual
Duration: 7 Sept 202110 Sept 2021

Publication series

ISSN (Print)1552-5244
ISSN (Electronic)2168-9253


ConferenceIEEE Cluster 2021
Internet address


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