ParaDox: Eliminating Voltage Margins via Heterogeneous Fault Tolerance

Sam Ainsworth, Lionel Zoubritzky, Alan Mycroft, Timothy M. Jones

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Providing reliability is becoming a challenge for chip manufacturers, faced with simultaneously trying to improve miniaturization, performance and energy efficiency. This leads to very large margins on voltage and frequency, designed to avoid errors even in the worst case, along with significant hardware expenditure on eliminating voltage spikes and other forms of transient error, causing considerable inefficiency in power consumption and performance.

We flip traditional ideas about reliability and performance around, by exploring the use of error resilience for power and performance gains. ParaMedic is a recent architecture that provides a solution for reliability with low overheads via automatic hardware error recovery, by splitting up checking on to many small cores in a heterogeneous multicore system with hardware logging support, but its design is based on the idea that errors are exceptional. We transform ParaMedic into ParaDox, which shows high performance in both error-intensive and scarce-error scenarios, thus allowing correct execution even when undervolted and overclocked.

Evaluation within error-intensive simulation environments confirms the error resilience of ParaDox and the low associated recovery cost. We estimate that compared to a non-resilient system with margins, ParaDox can reduce energy delay product by 15% through undervolting, while completely recovering from any induced errors.
Original languageEnglish
Title of host publication2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages520 - 532
Number of pages13
ISBN (Electronic)978-1-6654-2235-2
ISBN (Print)978-1-6654-4670-9
Publication statusPublished - 22 Apr 2021
EventThe 27th IEEE International Symposium on High-Performance Computer Architecture - Seoul, Korea, Republic of
Duration: 27 Feb 20213 Mar 2021
Conference number: 27

Publication series

ISSN (Print)1530-0897
ISSN (Electronic)2378-203X


ConferenceThe 27th IEEE International Symposium on High-Performance Computer Architecture
Abbreviated titleHPCA 2021
Country/TerritoryKorea, Republic of
Internet address

Keywords / Materials (for Non-textual outputs)

  • fault tolerance
  • microarchitecture
  • error detection
  • voltage margins


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