Parametric study of pulsed laser deposited (PLD) WSe2 2D transistors

S. C. Mbisike*, S. Seo, S. Lee, J. Phair, R. Cheung

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract / Description of output

A fabrication process for making large area transistors on pulsed laser deposited (PLD) WSe2 has been developed. Large films of WSe2 have been deposited via PLD technique on SiO2/Si substrate. Employing a mask-less lithography technique and using vapour XeF2 as an etchant, transistors of lengths (17, 83, 323 and 1000 μm) and widths (14 and 850 μm) have been fabricated. Electrical characterization of the transistors show that as the channel length (L) decreases, the magnitude of the drain-source current increases. In addition, the current across the transistor has been found to increase by increasing the channel width (W). Moreover, channels with large areas have been found to deliver substantially more drain-source current compared with smaller channel areas with similar W/L. A W/L ratio of 0.85 has been found to possess the highest drain current across the transistors fabricated. From the transfer length measurement (TLM), the sheet resistance and contact resistance of the device have been measured. Field effect mobility of the transistors have been calculated. Raman spectrum shows that PLD WSe2 possess similar quality as exfoliated WSe2. However, Photoluminescence (PL) spectrum and TLM results suggest the lack of bandgap in our 14-layer PLD WSe2.

Original languageEnglish
Article number111368
JournalMicroelectronic Engineering
Early online date27 May 2020
Publication statusPublished - 1 Jun 2020

Keywords / Materials (for Non-textual outputs)

  • Field-effect transistor (FET)
  • Large area 2D
  • PLD
  • WSe


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