Partitioning Data-parallel Programs for Heterogeneous MPSoCs: Time and Energy Design Space Exploration

Kiran Chandramohan, Michael F.P. O'Boyle

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Multiprocessor System-on-Chips(MPSoCs) are now widely used in embedded devices. MPSoCs typically contain a range of specialised processors. Alongside the CPU, there are microcontrollers, DSPs and other hardware accelerators. Programming these MPSoCs is difficult because of the difference in instruction-set architecture (ISA) and disjoint address spaces. In this paper we consider MPSoCs as a target for individual benchmarks. We examine how data-parallel programs can be optimally mapped to heterogeneous multicores for different criteria such as performance, power and energy. We investigate the partitioning of seven benchmarks taken from DSPstone, UTDSP and Polybench suites. Based on design space exploration we show that the best partition depends on compiler optimization level, program, input size and crucially optimization criteria. We develop a straightforward approach that attempts to select the best partitioning for a given program. On average it achieves speedups of 2.2x and energy improvements of 1.45x on the OMAP 4430 platform.
Original languageEnglish
Title of host publicationProceedings of the 2014 SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems
Place of PublicationNew York, NY, USA
PublisherACM
Pages73-82
Number of pages10
ISBN (Print)978-1-4503-2877-7
DOIs
Publication statusPublished - 2014

Keywords / Materials (for Non-textual outputs)

  • data-parallel, heterogeneous processor, partitioning, spmd

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