In the previous two chapters the architectures of two distinct families of vector processor were described. One, the CDC CYBER 205 uses operands stored in memory, whereas the other, the CRAY family, uses operands held in vector registers. Knowledge about such aspects of their design, together with knowledge about the clock periods of these machines, provides a limited picture of their performance potential. For example, before spending several millions of pounds (or dollars) on a high performance vector processor it is worth knowing just how well the machine is likely to perform on the types of problem for which it is intended, rather than knowing only the peak performance of the machine. The performance of all vector computers is the result of a combination of advanced architecture and advanced technology, both of which play an important rôle. Thus, when the performance of such machines is analysed it is useful to separate the architectural measurements from the technological measurements since this permits a comparison of the architectural quality of machines constructed from different technologies. This chapter therefore considers the ways in which the performance potential of vector processors can be quantified both from a technological and an architectural viewpoint, and begins by examining the raw hardware performance which derives from the use of pipelined vector instructions.
|Title of host publication||Architecture of High Performance Computers|
|Subtitle of host publication||Volume I: Uniprocessors and vector processors|
|Place of Publication||London|
|Publisher||Macmillan Education UK|
|Number of pages||13|
|Publication status||Published - 1989|