Performance of Weak Consistency Schemes on the DEC Alpha

The performance of a shared memory multiprocessor is largely dependent upon the model of shared memory this is presented to the user. Where the first such machines typically supported a very powerful model of shared memory, that of sequential consistency, more recent designs have often benefited from the use of weaker memory models. HOwever, there has been little standardisation between these weak models, and little practical work has been done to outline their possible implementations and performance. In the following, we consider the weakly consistent model of shared memory which is supported by the DEC Alpha, which promises to be a common building block for such multiprocessors in the future. We suggest possible implementations of the model, using both hardware and software techniques, and consider the subsequent performance of these schemes on a variety of application.