R. N. Ibbett, N. P. Topham

Research output: Chapter in Book/Report/Conference proceedingChapter


In any computer the execution of a single instruction requires various activities to be performed, such as instruction accessing, instruction interpretation, operand accessing and arithmetic. If separate hardware units carry out these activities their operations can be overlapped to give an increased rate of completion of instructions. This technique, first introduced in computers such as Atlas and Stretch, has become known as pipeline concurrency. In a pipelined computer several partially completed instructions are in progress concurrently, and although the time to complete any one instruction is still limited by the sum of the times for the various activities, the rate at which instructions progress through the pipeline is only limited by the time for an individual activity. In Atlas and Stretch the number of concurrent operations was of the order of four. In more recent designs the pipeline concurrency principle has been extended to several tens of instructions and used in both arithmetic and instruction processing units. In this chapter we shall discuss the principles of pipeline design, and then consider the actual design of the MU5 Primary Operand Unit as an example of instruction pipelining and Texas Instruments’ Advanced Scientific Computer (TI ASC) as an example of arithmetic pipelining. In addition we shall consider some techniques used in the IBM System/360 Model 195 to overcome the problems which arise in pipelined systems.
Original languageEnglish
Title of host publicationArchitecture of High Performance Computers
Subtitle of host publicationVolume I: Uniprocessors and vector processors
Place of PublicationLondon
PublisherMacmillan Education UK
Number of pages25
ISBN (Electronic)978-1-349-19757-6
ISBN (Print)978-0-333-46362-8
Publication statusPublished - 1989


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