Portable compiler optimisation across embedded programs and microarchitectures using machine learning

Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Grigori Fursin, Michael F.P. O'Boyle

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Building an optimising compiler is a difficult and time consuming task which must be repeated for each generation of a microprocessor. As the underlying microarchitecture changes from one generation to the next, the compiler must be retuned to optimise specifically for that new system. It may take several releases of the compiler to effectively exploit a processor's performance potential, by which time a new generation has appeared and the process starts again.

We address this challenge by developing a portable optimising compiler. Our approach employs machine learning to automatically learn the best optimisations to apply for any new program on a new microarchitectural configuration. It achieves this by learning a model off-line which maps a microarchitecture description plus the hardware counters from a single run of the program to the best compiler optimisation passes. Our compiler gains 67% of the maximum speedup obtainable by an iterative compiler search using 1000 evaluations. We obtain, on average, a 1.16x speedup over the highest default optimisation level across an entire microarchitecture configuration space, achieving a 4.3x speedup in the best case. We demonstrate the robustness of this technique by applying it to an extended microarchitectural space where we achieve comparable performance.
Original languageEnglish
Title of host publicationProceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 42)
Place of PublicationNew York, NY, USA
Number of pages11
ISBN (Print)978-1-60558-798-1
Publication statusPublished - 2009

Keywords / Materials (for Non-textual outputs)

  • architecture/compiler co-design
  • design-space exploration
  • machine learning


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