Power modelling and capping for heterogeneous ARM/FPGA SoCs

Y. Wu, J. Nunez-Yanez, R. Woods, D. S. Nikolopoulos

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Low-power processors and accelerators that were originally designed for the embedded systems market are emerging as building blocks for servers. Power capping has been actively explored as a technique to reduce the energy footprint of high-performance processors. The opportunities and limitations of power capping on the new low-power processor and accelerator ecosystem are less understood. This paper presents an efficient power capping and management infrastructure for heterogeneous SoCs based on hybrid ARM/FPGA designs. The infrastructure coordinates dynamic voltage and frequency scaling with task allocation on a customised Linux system for the Xilinx Zynq SoC. We present a compiler-assisted power model to guide voltage and frequency scaling, in conjunction with workload allocation between the ARM cores and the FPGA, under given power caps. The model achieves less than 5% estimation bias to mean power consumption. In an FFT case study, the proposed power capping schemes achieve on average 97.5% of the performance of the optimal execution and match the optimal execution in 87.5% of the cases, while always meeting power constraints.
Original languageEnglish
Title of host publicationField-Programmable Technology (FPT), 2014 International Conference on
Pages231-234
Number of pages4
DOIs
Publication statusPublished - 1 Dec 2014

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