Prism: The reincarnation of the VISIble COMPuter

For over thirty years, the United States Air Force Academy (USAFA) has used training aids to help students in our introductory digital course visualize computer architecture concepts by showing the inner workings of a simple microprocessor made primarily of the SSI and MSI chips which they were already familiar with. The original "EDUcational COMPuter" or EDUCOMP was replaced with a more visual and improved version, the "VISIble COMPuter" or VISICOMP in 1996³. Today, we have transitioned these hardware training aids to a hardware description language (HDL) implementation called the Programmable Reconfigurable Informational Simple Microcomputer or PRISM. PRISM is implemented on a Field-Programmable Gate Array (FPGA) while still retaining the original strengths of the EDUCOMP/VISICOMP computer architecture. PRISM is partitioned into the main subsystems of a computer (ALU, controller, memory, and input/output (I/O)). The controller is implemented as a simplistic, mealy state machine which allows students to see each step of the instruction cycle as an assembly language program is executed. PRISM's operation is visual to the student since: (1) each subsystem is built with small-scale-integration (SSI) and medium-scale-integration (MSI) components which the students have already learned in our course; (2) the status of the registers, signals, and busses are displayed directly on seven-segment displays; and (3) the students manually build and test each subsystem before integrating them into the final PRISM core to observe how each one works. After understanding the basics of the computer subsystems, the students then write their own assembly programs and translate them into machine code. They can then simulate their program running ahead of time or implement and run their programs in real time. This paper will discuss the features of PRISM and how it is used in the classroom.