Proximity coherence for chip multiprocessors

Nick Barrow-Williams, Christian Fensch, Simon Moore

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Many-core architectures provide an efficient way of harnessing the increasing numbers of transistors available in modern fabrication processes. While they are similar to multi-node systems, they exhibit different communication latency and storage characteristics, providing new design opportunities that were previously not feasible. Traditional cache coherence protocols, although often used in many-core designs, have been developed in the context of multinode systems. As such, they seldom take advantage of the new possibilities that many-core architectures offer.

We propose Proximity Coherence, a scheme in which L1 load misses are optimistically forwarded to nearby caches via new dedicated links rather than always being indirected via a directory structure. Such an optimization is made possible by the comparable cost of local cache accesses with the use of on-chip network resources. Coherency is maintained using lightweight graph structures embedded in the L1 caches. We compare our Proximity Coherence protocol to an existing directory-based MESI protocol using fullsystem simulations of a 32 core system. Our extension lowers the latency of L1 cache load misses by up to 32% while reducing the bytes transferred on the global on-chip interconnect by up to 19% for a range of parallel benchmarks. Employing Proximity Coherence provides execution time improvements of up to 13%, reduces cache hierarchy energy consumption by up to 30% and delivers a more efficient solution to the challenge of coherence in chip multiprocessors.
Original languageEnglish
Title of host publicationProceedings of the 19th international conference on Parallel architectures and compilation techniques
Place of PublicationNew York, NY, USA
Number of pages12
ISBN (Print)978-1-4503-0178-7
Publication statusPublished - 2010


  • Proximity Coherence
  • CMP
  • cache design
  • network-on-chip


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