Relocation-aware communication network for circuits on Xilinx FPGAs

Adewale Adetomi, Godwin Enemali, T. Arslan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The parallelism of hardware and the dynamic reconfigurability of FPGAs enable multiple hardware tasks to run concurrently, and also time-share resources by being swapped in and out of the device during runtime. More than ever before, these capabilities are being employed in systems with high-reliability requirements. To improve reliability, a method often used is circuit relocation. However, the static nature of conventional FPGA communication interconnects is a bane to flexible runtime relocation. This paper employs a novel network architecture to enable dynamic communication and thus improve the flexibility of circuit relocation. By using the clock infrastructure of the FPGA as the physical network links for tasks in a 4-node star network, we have shown that dynamic communication between relocatable circuits can be achieved without incurring any overheads of time and resources, save for only 32 slices used for the Network Interface.

Original languageEnglish
Title of host publication2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017
EditorsDiana Gohringer, Dirk Stroobandt, Nele Mentens, Marco Santambrogio, Jari Nurmi
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Electronic)9789090304281
DOIs
Publication statusPublished - 2 Oct 2017
Event27th International Conference on Field Programmable Logic and Applications, FPL 2017 - Gent, Belgium
Duration: 4 Sept 20176 Sept 2017

Publication series

Name2017 27th International Conference on Field Programmable Logic and Applications, FPL 2017

Conference

Conference27th International Conference on Field Programmable Logic and Applications, FPL 2017
Country/TerritoryBelgium
CityGent
Period4/09/176/09/17

Keywords / Materials (for Non-textual outputs)

  • bitstream relocation
  • CELOC
  • CERANoC
  • clock buffers
  • FPGA
  • inter-task communication
  • network on chip

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