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Abstract
Customised processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must take into account; die area and energy efficiency are equally important. Resource sharing during synthesis of instruction set extensions (ISEs) can reduce significantly the die area and energy consumption of a customised processor. This may increase the number of custom instructions that can be synthesized with a given area budget. Resource sharing involves combining the graph representations of two or more ISEs which contain a similar sub-graph. This coupling of multiple sub-graphs, if performed naively, can increase the latency of the extension instructions considerably. And yet, as we show in this paper, an appropriate level of resource sharing provides a significantly simpler design with only modest increases in average latency for extension instructions. Based on existing resource-sharing techniques, this study presents a new heuristic that controls the degree of resource sharing between a given set of custom instructions. Our main contributions are the introduction of a parametric method for exploring the trade-offs that can be achieved between instruction latency and implementation complexity, and the coupling of design-space exploration with fast area-delay models for the operators comprising each ISE. We present experimental evidence that our heuristic exposes a broad range of design points, allowing advantageous trade-offs between die area and latency to be found and exploited.
Original language | English |
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Title of host publication | Application Specific Processors, 2008. SASP 2008. Symposium on |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 7-13 |
Number of pages | 7 |
DOIs | |
Publication status | Published - 1 Jun 2008 |
Keywords
- instruction sets
- microprocessor chips
- resource allocation
- area-delay model
- custom instruction set extensions
- customised processor performance
- design-space exploration
- graph representation
- instruction latency
- resource sharing
- Application specific integrated circuits
- Application specific processors
- Computer aided instruction
- Computer architecture
- Costs
- Delay
- Energy efficiency
- Field programmable gate arrays
- Informatics
- Resource management
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Projects
- 1 Finished
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PASTA: Automated systhesis of high performance low power embedded systems.
Topham, N., Franke, B. & O'Boyle, M.
1/03/06 → 5/09/10
Project: Research