Restricting writes for energy-efficient hybrid cache in multi-core architectures

Sukarn Agarwal, Hemangee K. Kapoor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Emerging non-volatile memory technology Spin Transfer Torque Random Access Memory (STT-RAM) is a good candidate for the Last Level Cache (LLC) on account of high density, good scalability and low power consumption. However, expensive write operation reduces their chances as a replacement of SRAM. To handle these expensive write operations, an STT-RAM/SRAM hybrid cache architecture is proposed that reduces the number of writes and energy consumption of the STT-RAM region in the LLC by considering the existence of private blocks. Our approach allocates dataless entries for such kind of blocks when they are loaded in the LLC on a miss. We make changes in the conventional MESI protocol by adding new states to deal with the dataless entries. Experimental results using full system simulator shows 73% savings in write operations and 20% energy savings compared to an existing policy.
Original languageEnglish
Title of host publication2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Electronic)978-1-5090-3561-8
ISBN (Print)978-1-5090-3562-5
DOIs
Publication statusPublished - 24 Nov 2016
EventIFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2016 - Tallinn, Estonia
Duration: 26 Sept 201628 Sept 2016
https://ati.ttu.ee/vlsi-soc2016/index.php?page=7

Publication series

NameIFIP International Conference on Very Large Scale Integration (VLSI-SoC)
PublisherIEEE
ISSN (Electronic)2324-8440

Conference

ConferenceIFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2016
Abbreviated titleVLSI-SoC 2016
Country/TerritoryEstonia
CityTallinn
Period26/09/1628/09/16
Internet address

Keywords / Materials (for Non-textual outputs)

  • non-volatile memory
  • STT-RAM
  • hybrid cache
  • private blocks
  • expensive write
  • MESI protocol

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