Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches

S. Agarwal, H. K. Kapoor

Research output: Contribution to journalArticlepeer-review

Abstract / Description of output

Emerging nonvolatile memory technologies act as a prominent choice for the larger on-chip caches on account of high density, good scalability, and low static power consumption. However, costly write operations reduce their possibility as a successor of SRAM. To mitigate this problem, a spin-transfer torque random-access memory (STT-RAM)-SRAM hybrid cache architecture is proposed. In such cache architectures, allocation of a write-intensive block is the key challenge for energy efficiency. This paper presents a data allocation policy that reduces the number of writes and energy consumption of the STT-RAM region in the last-level cache by considering the existence of private blocks. Dataless entries are allocated in STT region for such private blocks, and actual data is written only when the block is written back from L1. Heavily written blocks are subsequently migrated to SRAM region. We also present a predictor that helps to redirect the write backs from L1 of dataless entries directly to SRAM region, depending on the predicted reuse-distance-aware write intensity. Experimental evaluation shows that this technique reduces the energy consumption by 34.3% (19.6%) and 23.3% (14.1%), respectively, over two existing techniques in the case of dual (quad) core system.
Original languageEnglish
Pages (from-to)1881-1894
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number10
Early online date7 Jun 2018
Publication statusPublished - 25 Sept 2018

Keywords / Materials (for Non-textual outputs)

  • nonvolatile memory
  • phase change random access memory
  • torque
  • protocols
  • magnetic tunneling
  • resistance


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