RRAM-based STDP network for edge computing in wearable/implantable devices

Yukai Shen, Shiwei Wang, Carolina Mora Lopez

Research output: Chapter in Book/Report/Conference proceedingConference contribution


With the technology advancement of wearable and implantable devices, the demand is increasing for low power computing circuits that allow processing of the acquired data on the edge to shorten the response time and save data bandwidth. Resistive-memory-based computing circuits have attracted broad interests due to their potential to implement low-power computing-in-memory macros and neuromorphic processors. This paper explores the hardware implementation of an artificial spiking neural network with the capability of online STDP learning by using a low-power analog CMOS circuit and a resistive random-access memory (RRAM) device. We examined the low power characteristics of the proposed circuit and its potential use for in situ signal processing, which holds promise for neural recording applications using implantable devices such as neural probes.
Original languageUndefined/Unknown
Title of host publication2021 18th International SoC Design Conference (ISOCC)
Number of pages2
Publication statusPublished - 25 Nov 2021
Event18th International SoC Design Conference - , Korea, Republic of
Duration: 6 Oct 20219 Oct 2021


Conference18th International SoC Design Conference
Abbreviated titleISOCC 2021
Country/TerritoryKorea, Republic of
Internet address

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