Projects per year
In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. Simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core 86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead.
|Title of host publication||Proceedings - 2011 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011|
|Number of pages||10|
|Publication status||Published - 7 Nov 2011|
|Event||2011 11th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011 - Samos, United Kingdom|
Duration: 18 Jul 2011 → 21 Jul 2011
|Conference||2011 11th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2011|
|Period||18/07/11 → 21/07/11|
FingerprintDive into the research topics of 'Scalable multi-core simulation using parallel dynamic binary translation'. Together they form a unique fingerprint.
- 1 Finished
Dynamic Adaptation in Hetrogeneous Multicore Embedded Processors
Haas, H., Franke, B., O'Boyle, M. & Topham, N.
1/11/10 → 30/07/14