Scheduling instructions with uncertain latencies in asynchronous architectures

D. K. Arvind, S. Sotelo-Salazar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper addresses the problem of scheduling instructions in micronet-based asynchronous processors (MAP), in which the latencies of the instructions are not precisely known. A PTD scheduler is proposed which minimises true dependencies, and results are compared with two list schedulers — the Gibbons and Muchnick scheduler, and a variation of the Balanced scheduler. The PTD scheduler has a lower time complexity and produces better quality schedules than the other two when applied twenty-three loop- and control-intensive benchmark programs.
Original languageEnglish
Title of host publicationEuro-Par'97 Parallel Processing
Subtitle of host publicationThird International Euro-Par Conference Passau, Germany, August 26–29, 1997 Proceedings
EditorsChristian Lengauer, Martin Griebl, Sergei Gorlatch
Place of PublicationBerlin, Heidelberg
PublisherSpringer Berlin Heidelberg
Pages771-778
Number of pages8
ISBN (Print)978-3-540-69549-3
DOIs
Publication statusPublished - 1997

Publication series

NameLecture Notes in Computer Science
PublisherSpringer Berlin Heidelberg
Volume1300
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

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