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Seamless Acceleration of Fortran Intrinsics via AMD AI Engines

Research output: Contribution to conference › Abstract › peer-review

Abstract

A major challenge that the HPC community faces is how to continue delivering the performance demanded by scientific programmers, whilst meeting an increased emphasis on sustainable operations. Specialised architectures, such as FPGAs and AMD's AI Engines (AIEs), have been demonstrated to provide significant energy efficiency advantages, however a major challenge is that to most effectively program these architectures requires significant expertise and investment of time which is a major blocker.

Fortran in the lingua franca of scientific computing, and in this paper we explore automatically accelerating Fortran intrinsics via the AIEs in AMD's Ryzen AI CPU. Leveraging the open source Flang compiler and MLIR ecosystem, we describe an approach that lowers the MLIR linear algebra dialect to AMD's AIE dialects, and demonstrate that for suitable workloads the AIEs can provide significant performance advantages over the CPU without any code modifications required by the programmer.
Original languageEnglish
Pages185
DOIs
Publication statusPublished - 27 Feb 2025
EventACM/SIGDA International Symposium on Field-Programmable Gate Arrays - Monterey, United States
Duration: 27 Feb 2025 → 1 Mar 2025
https://www.isfpga.org/

Conference

ConferenceACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Abbreviated titleISFPGA
Country/TerritoryUnited States
CityMonterey
Period27/02/25 → 1/03/25
Internet address

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