Segment gating for static energy reduction in networks-on-chip

K.C. Hale, B. Grot, S.W. Keckler

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Chip multiprocessors (CMPs) have emerged as a primary vehicle for overcoming the limitations of uniprocessor scaling, with power constraints now representing a key factor of CMP design. Recent studies have shown that the on-chip interconnection network (NOC) can consume as much as 36% of overall chip power. To date, researchers have employed several techniques to reduce power consumption in the network, including the use of on/off links by means of power gating. However, many of these techniques target dynamic power, and those that consider static power focus exclusively on flit buffers. In this paper, we aim to reduce static power consumption through a comprehensive approach that targets buffers, switches, arbitration units, and links. We establish an optimal power-down scheme which we use as an upper bound to evaluate several static policies on synthetic traffic patterns. We also evaluate dynamic utilization-aware power-down policies using traces from the PARSEC benchmark suite. We show that both static and dynamic policies can greatly reduce static energy at low injection rates with only minimal increases in dynamic energy and latency.
Original languageEnglish
Title of host publicationNetwork on Chip Architectures, 2009. NoCArc 2009. 2nd International Workshop on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages6
ISBN (Print)978-1-60558-774-5
Publication statusPublished - 1 Dec 2009


  • integrated circuit design
  • integrated circuit interconnections
  • network-on-chip
  • power consumption
  • PARSEC benchmark
  • chip multiprocessors
  • on-chip interconnection network
  • optimal power-down scheme
  • segment gating
  • static energy reduction
  • static power consumption
  • Computer networks
  • Delay
  • Energy consumption
  • Logic
  • Multiprocessor interconnection networks
  • Network-on-a-chip
  • Power dissipation
  • Switches
  • Upper bound
  • Vehicle dynamics
  • Interconnection networks
  • leakage power
  • network-on-chip (NOC)
  • power optimization


Dive into the research topics of 'Segment gating for static energy reduction in networks-on-chip'. Together they form a unique fingerprint.

Cite this