Abstract / Description of output
A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.
| Original language | English |
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| Patent number | US8552482B2 |
| IPC | H01L31/062 |
| Filing date | 10/07/08 |
| Publication status | Published - 16 Aug 2012 |