Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

H. Kim, B. Grot, P. V. Gratz, D. A. Jiménez

Research output: Contribution to journalArticlepeer-review

Abstract / Description of output

As processor chips become increasingly parallel, an efficient communication substrate is critical for meeting performance and energy targets. In this work, we target the root cause of network energy consumption through techniques that reduce link and router-level switching activity. We specifically focus on memory subsystem traffic, as it comprises the bulk of NoC load in a CMP. By transmitting only the flits that contain words predicted useful using a novel spatial locality predictor, our scheme seeks to reduce network activity. We aim to further lower NoC energy through microarchitectural mechanisms that inhibit datapath switching activity for unused words in individual flits. Using simulation-based performance studies and detailed energy models based on synthesized router designs and different link wire types, we show that 1) the prediction mechanism achieves very high accuracy, with an average rate of false-unused prediction of just 2.5 percent; 2) the combined NoC energy savings enabled by the predictor and microarchitectural support is 36 percent, on average, and up to 57 percent in the best case; and 3) there is no system performance penalty as a result of this technique.
Original languageEnglish
Pages (from-to)543-556
Number of pages14
JournalIEEE Transactions on Computers
Issue number3
Publication statusPublished - Mar 2014


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