Spidergon STNoC Design Flow

Florentine Dubois, Jose Cano Reyes, Marcello Coppola, Jose Flich, Frederic Petrot

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.
Original languageEnglish
Title of host publicationNOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Place of PublicationNew York, NY, USA
Number of pages2
ISBN (Print)978-1-4503-0720-8
Publication statusPublished - 2011

Keywords / Materials (for Non-textual outputs)

  • architecture, design flow, design space exploration, network on chips, performance estimation, spidergon STNoC, synthesis


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