Spidergon STNoC Design Flow

Florentine Dubois; Jose Cano Reyes; Marcello Coppola; Jose Flich; Frederic Petrot

doi:10.1145/1999946.1999994

Spidergon STNoC Design Flow

Florentine Dubois, Jose Cano Reyes, Marcello Coppola, Jose Flich, Frederic Petrot

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.

Original language	English
Title of host publication	NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Place of Publication	New York, NY, USA
Publisher	ACM
Pages	267-268
Number of pages	2
ISBN (Print)	978-1-4503-0720-8
DOIs	https://doi.org/10.1145/1999946.1999994
Publication status	Published - 2011

Keywords / Materials (for Non-textual outputs)

architecture, design flow, design space exploration, network on chips, performance estimation, spidergon STNoC, synthesis

Access to Document

10.1145/1999946.1999994

http://dl.acm.org/citation.cfm?doid=1999946.1999994

Cite this

@inproceedings{42838e6180fb43a391d9ea0b0d6a6279,

title = "Spidergon STNoC Design Flow",

abstract = "In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.",

keywords = "architecture, design flow, design space exploration, network on chips, performance estimation, spidergon STNoC, synthesis",

author = "Florentine Dubois and {Cano Reyes}, Jose and Marcello Coppola and Jose Flich and Frederic Petrot",

year = "2011",

doi = "10.1145/1999946.1999994",

language = "English",

isbn = "978-1-4503-0720-8",

pages = "267--268",

booktitle = "NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip",

publisher = "ACM",

}

TY - GEN

T1 - Spidergon STNoC Design Flow

AU - Dubois, Florentine

AU - Cano Reyes, Jose

AU - Coppola, Marcello

AU - Flich, Jose

AU - Petrot, Frederic

PY - 2011

Y1 - 2011

N2 - In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.

AB - In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.

KW - architecture, design flow, design space exploration, network on chips, performance estimation, spidergon STNoC, synthesis

U2 - 10.1145/1999946.1999994

DO - 10.1145/1999946.1999994

M3 - Conference contribution

SN - 978-1-4503-0720-8

SP - 267

EP - 268

BT - NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

PB - ACM

CY - New York, NY, USA

ER -

Spidergon STNoC Design Flow

Abstract

Keywords / Materials (for Non-textual outputs)

Access to Document

Fingerprint

Cite this