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This paper presents some circuitry for use within a visual-processing depth-recovery algorithm based upon spike timing. The accuracy of the depth calculation relies on a prediction which, when implemented in analogue VLSI, will be degraded by transistor mismatch. An adaptive circuit based on Spike Timing Dependent Plasticity (STDP) was designed to reduce the effects of VLSI process variations on the algorithm's performance. Simulation Results for the circuitry, designed using a 0.35μm process, are reported.
|Title of host publication||Proceedings - IEEE International Symposium on Circuits and Systems|
|Number of pages||4|
|Publication status||Published - 1 Jan 2006|