Static scheduling of instructions on micronet-based asynchronous processors

D. K. Arvind, V. E. F. Rebello

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper investigates issues which impinge on the design of static instruction schedulers for micronet-based asynchronous processor (MAP) architectures. The micronet model exposes both temporal and spatial concurrency within a processor. A list scheduling algorithm is described which has been optimised with MAP-specific heuristics. Their performance on some program graphs are presented and conclusions are drawn on the suitability of MAP as targets for ILP compilers
Original languageEnglish
Title of host publicationAdvanced Research in Asynchronous Circuits and Systems, 1996. Proceedings., Second International Symposium on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages12
ISBN (Print)0-8186-7298-6
Publication statusPublished - 1 Mar 1996


  • parallel architectures
  • processor scheduling
  • scheduling
  • Asynchronous Processor Architecture
  • Instruction-level Parallelism
  • MAP-specific heuristics
  • asynchronous processors
  • list scheduling algorithm
  • micronet mode
  • micronets
  • program graphs
  • static instruction schedulers
  • static scheduling
  • Computer science
  • Concurrent computing
  • Delay
  • Hardware
  • Pipelines
  • Process design
  • Processor scheduling
  • Program processors
  • Reduced instruction set computing
  • Scheduling algorithm


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