Statistical SPICE analysis of a 0.18μm CMOS digital/analog technology during process development

N. S. Rankin*, C. Ng, L. S. Ee, F. Boyland, E. Quek, L. Y. Keung, A. J. Walton, M. Redford

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract / Description of output

This paper gives details of a methodology to extract statistical SPICE models on a developing deep sub micron CMOS technology. The approach uses a TCAD framework which integrates process, device, parameter extraction, and statistics software. The TCAD tools are calibrated by physical and electrical measurements on transistor test structures with different channel lengths. Once calibrated, a Monte Carlo experiment is run on all process control input parameters with realistic variations and the results then compared to in-line and E-test distributions. When satisfied that the variance in TCAD and measured distributions match, the framework can be used to extract BSIM3v3.2 parameters to generate statistical models. Multivariate statistics is used to determine the key process parameters which need to be controlled in-line to minimize device variation. This methodology is demonstrated using Chartered Semiconductor Manufacturing Ltd's 0.18μm CMOS core logic technology.

Original languageEnglish
Pages19-23
Number of pages5
Publication statusPublished - 1 Jan 2001
EventICMTS 2001. 2001 International Conference on Microelectronic Test Structures - Kobe, Japan
Duration: 19 Mar 200122 Mar 2001

Conference

ConferenceICMTS 2001. 2001 International Conference on Microelectronic Test Structures
Country/TerritoryJapan
CityKobe
Period19/03/0122/03/01

Fingerprint

Dive into the research topics of 'Statistical SPICE analysis of a 0.18μm CMOS digital/analog technology during process development'. Together they form a unique fingerprint.

Cite this