Statistical SPICE Analysis of a 0.18*mm CMOS Digital/Analog Technology During Process Development

N. S. Rankin, C. Ng, L. S. Ee, F. Boyland, E. Quek, L. Y. Keung, A. J. Walton, M. Redford

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	Undefined/Unknown
Title of host publication	IEEE International Conference on Microelectronic Test Structures
Pages	5
Number of pages	1
Publication status	Published - 2001

Cite this

@inproceedings{b5073f8df57b4a1fbf4aaa26435fd753,

title = "Statistical SPICE Analysis of a 0.18*mm CMOS Digital/Analog Technology During Process Development",

author = "Rankin, {N. S.} and C. Ng and Ee, {L. S.} and F. Boyland and E. Quek and Keung, {L. Y.} and Walton, {A. J.} and M. Redford",

year = "2001",

language = "Undefined/Unknown",

pages = "5",

booktitle = "IEEE International Conference on Microelectronic Test Structures",

}

TY - GEN

T1 - Statistical SPICE Analysis of a 0.18*mm CMOS Digital/Analog Technology During Process Development

AU - Rankin, N. S.

AU - Ng, C.

AU - Ee, L. S.

AU - Boyland, F.

AU - Quek, E.

AU - Keung, L. Y.

AU - Walton, A. J.

AU - Redford, M.

PY - 2001

Y1 - 2001

M3 - Conference contribution

SP - 5

BT - IEEE International Conference on Microelectronic Test Structures

ER -