Synthetic Trace-Driven Simulation of Cache Memory

R. Hassan, A. Harris, N. Topham, A. Efthymiou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The widening gap between CPU and memory speed has made caches an integral feature of modern high- performance processors. The high degree of configurability of cache memory can require extensive design space exploration and is generally performed using execution-driven or trace-driven simulation. Execution-driven simulators can be highly accurate but require a detailed development flow and may impose performance costs. Trace-driven simulators are an efficient alternative but maintaining large traces can present storage and portability problems. We propose a distribution-driven trace generation methodology as an alternative to traditional execution- and trace- driven simulation. An adaptation of the Least Recently Used Stack Model is used to concisely capture the key locality features in a trace and a two-state Markov chain model is used for trace generation. Simulation and analysis of a variety of embedded application traces demonstrate the cacheability characteristics of the synthetic traces are generally very well preserved and similar to their real trace, and we also highlight the potential performance improvement over ISA emulation.
Original languageEnglish
Title of host publicationAdvanced Information Networking and Applications Workshops, 2007, AINAW '07. 21st International Conference on
Pages764-771
Number of pages8
Volume1
DOIs
Publication statusPublished - 1 May 2007

Keywords

  • Markov processes
  • cache storage
  • CPU
  • Least Recently Used Stack Model
  • cache memory
  • key locality features
  • memory speed
  • synthetic trace-driven simulation
  • two-state Markov chain model
  • Analytical models
  • Cache memory
  • Cost function
  • Delay
  • Emulation
  • Informatics
  • Instruction sets
  • Performance analysis
  • Space exploration
  • Timing

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