Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets

Sukarn Agarwal, Hemangee K. Kapoor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

High density and low static power exhibited by nonvolatile technologies (NVM) have made them popular candidates in the memory hierarchy, including caches. Writes within a cache set are governed by the access pattern as well as replacement policies, leading to a large write variation. This variation is of concern as it leads to early breakdown of the NVM cells due to large writes thus reducing the effective lifetime. This paper presents a technique to improve the lifetime of non-volatile caches by reducing the inter-set write variation. Our policy partitions the cache sets into groups called fellow groups. Every set has two logical parts: Normal and Reserved. Sets within a fellow group can use the reserved parts from their fellow sets to distribute the writes uniformly. Experimental results using full system simulation show that the proposed technique shows significant reduction in inter-set write variation over the baseline and existing technique.
Original languageEnglish
Title of host publication2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Electronic)978-1-5386-2880-5
ISBN (Print)978-1-5386-2881-2
DOIs
Publication statusPublished - 14 Dec 2017
Event25th IFIP/IEEE International Conference on Very Large Scale Integration - Abu Dhabi, United Arab Emirates
Duration: 23 Oct 201725 Oct 2017
Conference number: 25

Publication series

Name2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
PublisherIEEE
ISSN (Electronic)2324-8440

Conference

Conference25th IFIP/IEEE International Conference on Very Large Scale Integration
Abbreviated titleVLSI-SoC 2017
Country/TerritoryUnited Arab Emirates
CityAbu Dhabi
Period23/10/1725/10/17

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