Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets

Sukarn Agarwal; Hemangee K. Kapoor

doi:10.1109/VLSI-SoC.2017.8203453

Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets

Sukarn Agarwal, Hemangee K. Kapoor

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

High density and low static power exhibited by nonvolatile technologies (NVM) have made them popular candidates in the memory hierarchy, including caches. Writes within a cache set are governed by the access pattern as well as replacement policies, leading to a large write variation. This variation is of concern as it leads to early breakdown of the NVM cells due to large writes thus reducing the effective lifetime. This paper presents a technique to improve the lifetime of non-volatile caches by reducing the inter-set write variation. Our policy partitions the cache sets into groups called fellow groups. Every set has two logical parts: Normal and Reserved. Sets within a fellow group can use the reserved parts from their fellow sets to distribute the writes uniformly. Experimental results using full system simulation show that the proposed technique shows significant reduction in inter-set write variation over the baseline and existing technique.

Original language	English
Title of host publication	2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Publisher	Institute of Electrical and Electronics Engineers
Pages	1-6
Number of pages	6
ISBN (Electronic)	978-1-5386-2880-5
ISBN (Print)	978-1-5386-2881-2
DOIs	https://doi.org/10.1109/VLSI-SoC.2017.8203453
Publication status	Published - 14 Dec 2017
Event	25th IFIP/IEEE International Conference on Very Large Scale Integration - Abu Dhabi, United Arab Emirates Duration: 23 Oct 2017 → 25 Oct 2017 Conference number: 25

Publication series

Name	2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Publisher	IEEE
ISSN (Electronic)	2324-8440

Conference

Conference	25th IFIP/IEEE International Conference on Very Large Scale Integration
Abbreviated title	VLSI-SoC 2017
Country/Territory	United Arab Emirates
City	Abu Dhabi
Period	23/10/17 → 25/10/17

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https://ieeexplore.ieee.org/document/8203453Licence: All Rights Reserved

Cite this

Agarwal, S., & Kapoor, H. K. (2017). Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. In 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) (pp. 1-6). (2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/VLSI-SoC.2017.8203453

Agarwal, Sukarn ; Kapoor, Hemangee K. / Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). Institute of Electrical and Electronics Engineers, 2017. pp. 1-6 (2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)).

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title = "Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets",

abstract = "High density and low static power exhibited by nonvolatile technologies (NVM) have made them popular candidates in the memory hierarchy, including caches. Writes within a cache set are governed by the access pattern as well as replacement policies, leading to a large write variation. This variation is of concern as it leads to early breakdown of the NVM cells due to large writes thus reducing the effective lifetime. This paper presents a technique to improve the lifetime of non-volatile caches by reducing the inter-set write variation. Our policy partitions the cache sets into groups called fellow groups. Every set has two logical parts: Normal and Reserved. Sets within a fellow group can use the reserved parts from their fellow sets to distribute the writes uniformly. Experimental results using full system simulation show that the proposed technique shows significant reduction in inter-set write variation over the baseline and existing technique.",

author = "Sukarn Agarwal and Kapoor, \{Hemangee K.\}",

year = "2017",

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day = "14",

doi = "10.1109/VLSI-SoC.2017.8203453",

language = "English",

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series = "2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)",

publisher = "Institute of Electrical and Electronics Engineers",

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booktitle = "2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)",

address = "United States",

note = "25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 ; Conference date: 23-10-2017 Through 25-10-2017",

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Agarwal, S & Kapoor, HK 2017, Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. in 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Institute of Electrical and Electronics Engineers, pp. 1-6, 25th IFIP/IEEE International Conference on Very Large Scale Integration, Abu Dhabi, United Arab Emirates, 23/10/17. https://doi.org/10.1109/VLSI-SoC.2017.8203453

Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. / Agarwal, Sukarn; Kapoor, Hemangee K.
2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). Institute of Electrical and Electronics Engineers, 2017. p. 1-6 (2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets

AU - Agarwal, Sukarn

AU - Kapoor, Hemangee K.

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PY - 2017/12/14

Y1 - 2017/12/14

N2 - High density and low static power exhibited by nonvolatile technologies (NVM) have made them popular candidates in the memory hierarchy, including caches. Writes within a cache set are governed by the access pattern as well as replacement policies, leading to a large write variation. This variation is of concern as it leads to early breakdown of the NVM cells due to large writes thus reducing the effective lifetime. This paper presents a technique to improve the lifetime of non-volatile caches by reducing the inter-set write variation. Our policy partitions the cache sets into groups called fellow groups. Every set has two logical parts: Normal and Reserved. Sets within a fellow group can use the reserved parts from their fellow sets to distribute the writes uniformly. Experimental results using full system simulation show that the proposed technique shows significant reduction in inter-set write variation over the baseline and existing technique.

AB - High density and low static power exhibited by nonvolatile technologies (NVM) have made them popular candidates in the memory hierarchy, including caches. Writes within a cache set are governed by the access pattern as well as replacement policies, leading to a large write variation. This variation is of concern as it leads to early breakdown of the NVM cells due to large writes thus reducing the effective lifetime. This paper presents a technique to improve the lifetime of non-volatile caches by reducing the inter-set write variation. Our policy partitions the cache sets into groups called fellow groups. Every set has two logical parts: Normal and Reserved. Sets within a fellow group can use the reserved parts from their fellow sets to distribute the writes uniformly. Experimental results using full system simulation show that the proposed technique shows significant reduction in inter-set write variation over the baseline and existing technique.

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DO - 10.1109/VLSI-SoC.2017.8203453

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BT - 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

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T2 - 25th IFIP/IEEE International Conference on Very Large Scale Integration

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Agarwal S, Kapoor HK. Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. In 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC). Institute of Electrical and Electronics Engineers. 2017. p. 1-6. (2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)). doi: 10.1109/VLSI-SoC.2017.8203453

Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets

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