This paper presents a full wafer test structure, designed to quantify the effect of seed layer thickness and conductivity on the plating uniformity of patterned electroplated structures. The test structure enables the effect of IR drop on the electroplated film to be evaluated and provides information to help facilitate the optimisation of seed layer thickness.
|Title of host publication||Proceedings of the 2018 IEEE International Conference on Microelectronic Test Structures|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Publication status||Published - 19 Mar 2018|