Test structures for the characterisation of MEMS and CMOS integration technology

H. Lin; A.J. Walton; C.C. Dunare; Tom Stevenson; A.M. Gundlach; S. Smith; A.S. Bunting

doi:10.1109/ICMTS.2006.1614292

Test structures for the characterisation of MEMS and CMOS integration technology

H. Lin, A.J. Walton, C.C. Dunare, Tom Stevenson, A.M. Gundlach, S. Smith, A.S. Bunting

Research output: Chapter in Book/Report/Conference proceeding › Other chapter contribution

Abstract / Description of output

Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to create an integrated system. This involves using low temperature bonding along with CMP planarisation and wafer thinning. The last step in the integration process is bringing the electrical connections to the top surface and the creation of interconnect between the wafers. Test structures to evaluate this process have been designed and fabricated resulting in 7 - 9 Ω resistances for via chain structures. Via contact resistances of 6 × 10 Ω.cm were measured using Kelvin test structures.

Original language	English
Title of host publication	IEEE International Conference on Microelectronic Test Structures
Pages	143-148
Number of pages	6
Volume	2006
DOIs	https://doi.org/10.1109/ICMTS.2006.1614292
Publication status	Published - Mar 2006
Event	International Conference on Microelectronic Test Structures (ICMTS 2006) - Austin Duration: 6 Mar 2006 → 9 Mar 2006

Conference

Conference	International Conference on Microelectronic Test Structures (ICMTS 2006)
City	Austin
Period	6/03/06 → 9/03/06

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10.1109/ICMTS.2006.1614292

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@inbook{341c792373364c4b82f16e7650fc76ee,

title = "Test structures for the characterisation of MEMS and CMOS integration technology",

abstract = "Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to create an integrated system. This involves using low temperature bonding along with CMP planarisation and wafer thinning. The last step in the integration process is bringing the electrical connections to the top surface and the creation of interconnect between the wafers. Test structures to evaluate this process have been designed and fabricated resulting in 7 - 9 Ω resistances for via chain structures. Via contact resistances of 6 × 10 Ω.cm were measured using Kelvin test structures.",

author = "H. Lin and A.J. Walton and C.C. Dunare and Tom Stevenson and A.M. Gundlach and S. Smith and A.S. Bunting",

year = "2006",

month = mar,

doi = "10.1109/ICMTS.2006.1614292",

language = "English",

volume = "2006",

pages = "143--148",

booktitle = "IEEE International Conference on Microelectronic Test Structures",

note = "International Conference on Microelectronic Test Structures (ICMTS 2006) ; Conference date: 06-03-2006 Through 09-03-2006",

}

Lin, H, Walton, AJ, Dunare, CC, Stevenson, T, Gundlach, AM, Smith, S & Bunting, AS 2006, Test structures for the characterisation of MEMS and CMOS integration technology. in IEEE International Conference on Microelectronic Test Structures. vol. 2006, pp. 143-148, International Conference on Microelectronic Test Structures (ICMTS 2006), Austin, 6/03/06. https://doi.org/10.1109/ICMTS.2006.1614292

TY - CHAP

T1 - Test structures for the characterisation of MEMS and CMOS integration technology

AU - Lin, H.

AU - Walton, A.J.

AU - Dunare, C.C.

AU - Stevenson, Tom

AU - Gundlach, A.M.

AU - Smith, S.

AU - Bunting, A.S.

PY - 2006/3

Y1 - 2006/3

N2 - Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to create an integrated system. This involves using low temperature bonding along with CMP planarisation and wafer thinning. The last step in the integration process is bringing the electrical connections to the top surface and the creation of interconnect between the wafers. Test structures to evaluate this process have been designed and fabricated resulting in 7 - 9 Ω resistances for via chain structures. Via contact resistances of 6 × 10 Ω.cm were measured using Kelvin test structures.

AB - Test structures have been used to demonstrate the feasibility of bonding MEMS and CMOS wafers to create an integrated system. This involves using low temperature bonding along with CMP planarisation and wafer thinning. The last step in the integration process is bringing the electrical connections to the top surface and the creation of interconnect between the wafers. Test structures to evaluate this process have been designed and fabricated resulting in 7 - 9 Ω resistances for via chain structures. Via contact resistances of 6 × 10 Ω.cm were measured using Kelvin test structures.

UR - http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-33749536255&md5=f94945979c3c6ecc94c1d591909a2533

U2 - 10.1109/ICMTS.2006.1614292

DO - 10.1109/ICMTS.2006.1614292

M3 - Other chapter contribution

AN - SCOPUS:33749536255

VL - 2006

SP - 143

EP - 148

BT - IEEE International Conference on Microelectronic Test Structures

T2 - International Conference on Microelectronic Test Structures (ICMTS 2006)

Y2 - 6 March 2006 through 9 March 2006

ER -

Test structures for the characterisation of MEMS and CMOS integration technology

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