Test structures to characterize a novel circuit fabrication technique that uses offset lithography

A. J. Walton*, J. T.M. Stevenson, M. Fallon, P. S.A. Evans, B. J. Ramsey, D. Harrison

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper reports on the use of microelectronic test structures to characterize a novel fabrication technique for thin-film electronic circuit boards. In this technology circuit tracks are formed on paper-like substrates by depositing films of a metal-loaded ink via a standard lithographic printing process. Sheet resistance and linewidth are electrically evaluated and these compared with optical and surface profiling measurements.

Original languageEnglish
Pages39-44
Number of pages6
Publication statusPublished - 1 Jan 1998
EventProceedings of the 1998 IEEE International Conference on Microelectronic Test Structures - Kanazawa, Jpn
Duration: 23 Mar 199826 Mar 1998

Conference

ConferenceProceedings of the 1998 IEEE International Conference on Microelectronic Test Structures
CityKanazawa, Jpn
Period23/03/9826/03/98

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